| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress an increase in a packaging area when laminating a plurality of memory chips. <P>SOLUTION: A first memory chip 103a and a second memory chip 103b mounted on one surface of a packaging substrate 101 in this order have a rectangular planar shape, and include a plurality of electrode pads arranged only in a line along one rectangular side. An electrode pad line of the second memory chip 103b is arranged in parallel with the electrode pad line of the first memory chip 103a. A chip select pad is arranged at one end of the electrode pad line. The control, address, or data pad 113a of the first memory chip 103a is wire-bonded to a first stitch 109 arranged in a line along one rectangular side; and a chip select pad 121a and a chip select pad 121b are wire-bonded to a second stitch 111 arranged in a line along an adjacent side at the side of the chip select pad 121a. <P>COPYRIGHT: (C)2009,JPO&INPIT |
