发明名称 CLOCK RECOVERY CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit capable of reducing the influence of noise even if the noise is mixed with data to be serially transmitted. <P>SOLUTION: The clock recovery circuit 1 for selecting and outputting a clock having a rise in the middle (center) of a change point of inputted serial data among multiphase clocks generated from a reference clock by a multiphase clock generating part 5, is provided with a noise canceling part 3 for eliminating a noise component of predetermined signal width or below after detecting an edge of the input data, and the clock is outputted to a clock selecting part 4 while preventing clock switching due to the noise component from occurring. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008236179(A) 申请公布日期 2008.10.02
申请号 JP20070070790 申请日期 2007.03.19
申请人 RICOH CO LTD 发明人 AKIYAMA KAZUHITO
分类号 H04L7/02;G06F13/38;H03L7/00 主分类号 H04L7/02
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