发明名称 FAULT TOLERANT COMPUTER SYSTEM AND DATA TRANSMISSION CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide an I/O transaction storage buffer of a small capacity which permits deviation of an issuance period and order of I/O transactions from a CPU and prevents deterioration of throughput in a fault tolerant computer. SOLUTION: In a fault tolerant computer, a buffer area for accumulating CPU outputs is divided and dedicated areas (220, 220', 220''of Fig.3) for respective I/O targets and shared areas 260 and 260' are prepared. Speed reduction is avoided by certainly permitting order passing between I/O targets in the dedicated areas and substantially enlarging a buffer capacity for each I/O target by a shared area. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008234141(A) 申请公布日期 2008.10.02
申请号 JP20070070622 申请日期 2007.03.19
申请人 NEC CORP 发明人 MIZUTANI FUMITOSHI
分类号 G06F11/18;G06F13/38 主分类号 G06F11/18
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