发明名称 SEMICONDUCTOR MEMORY, MEMORY CONTROLLER AND SYSTEM, AND METHOD OF OPERATING SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To refresh a memory without lowering the access efficiency while minimizing an increase of the circuit scale. SOLUTION: When a main block address MRAD held in a main refresh-address counter MRAC coincides with an access block address BAD corresponding to an access request, counter values are transmitted to a sub-refresh address counter SRAC. Then, the sub-refresh address counter SRAC operates in preference to the main refresh-address counter MRAC until reaching the final value. Thus, access and refresh operations can be simultaneously executed without interfering each other. As a result, it is possible to reduce the circuit scale and refresh the memory without lowering the access efficiency. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008234699(A) 申请公布日期 2008.10.02
申请号 JP20070068682 申请日期 2007.03.16
申请人 FUJITSU LTD 发明人 KAWABATA KUNINORI
分类号 G11C11/406;G11C11/403 主分类号 G11C11/406
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