发明名称 High-Speed Receiver Architecture
摘要 A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
申请公布号 US2008240325(A1) 申请公布日期 2008.10.02
申请号 US20080056084 申请日期 2008.03.26
申请人 CLARIPHY COMMUNICATIONS, INC. 发明人 AGAZZI OSCAR E.;CRIVELLI DIEGO E.;CARRER HUGO S.;HUEDA MARIO R.;LUNA GERMAN C.;GRACE CARL
分类号 H04L7/00 主分类号 H04L7/00
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