发明名称 METHOD OF FLATTENING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FLATTENING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a method of flattening a semiconductor device which can suppress irregularity in a chip while minimizing a quantity of dummy pattern insertion by removing part of a dummy pattern, and also a semiconductor device flattening system. SOLUTION: In the method of flattening a semiconductor device which introduces the dummy pattern as not to electrically function except for grooves formed as wiring with use of a simulation server during manufacture of the semiconductor device, the dummy pattern having a prescribed spacing is introduced in all area other than wiring and other locations where such a pattern as to electrically function is present on design data, and then the dummy pattern on the design data is removed from such a location that a film thickness is predicted to become large after CMP process to manufacture a shadow mask using the design data after the dummy pattern is removed. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008235623(A) 申请公布日期 2008.10.02
申请号 JP20070073961 申请日期 2007.03.22
申请人 RENESAS TECHNOLOGY CORP 发明人 OTAKE ATSUSHI
分类号 H01L21/3205 主分类号 H01L21/3205
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