| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the load on a designer by efficiently designing a peripheral pattern configuration (the width of a peripheral region), suitable to the kind of a semiconductor chip and to lower the cost by finding the effective number of chips on a wafer and a width with which dicing conditions are most advantageous. <P>SOLUTION: The design method for the semiconductor chip which is manufactured on the wafer and has a core region and a peripheral region, where the size of the semiconductor chip is determined, by setting dicing conditions corresponding to the wafer and semiconductor chip (ST1), setting conditions for a mark to be disposed in the peripheral region of the semiconductor chip (ST2), and extracting a block configuration of the semiconductor chip in an exposure shot (ST3). <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
