| 摘要 |
An integrated memory circuit device having a memory cell array (102) including a plurality of bit lines (e.g., 32a, 32b) and a plurality of bit line segments (e.g., 32a1, 32b1) wherein each bit line segment is coupled to an associated bit line (32a, 32b). The memory cell array (102) further includes a plurality of memory cells (12), wherein each memory cell (12) includes a transistor (14) having a first region, a second region, a body region, and a gate coupled to an associated word line (28) via an associated word line segment. A first group of memory cells (12) is coupled to the first bit line (32a) via the first bit line segment (32a1) and a second group of memory cells (12) is coupled to the second bit line (32b) via the second bit line segment (32b1). A plurality of isolation circuits (104), disposed between each bit line segment (32a1, 32b1) and its associated bit line (32a, 32b), responsively connect the associated bit line segment to or disconnect the associated bit line segment (32a1, 32b1) from the associated bit line (32a, 32b). |
