| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock data recovery (CDR) circuit of a serial data interface, which is suitable for making into an LSI and is capable of setting characteristics equal to the ones when using the conventional PLL. <P>SOLUTION: The CDR circuit of this invention comprises: a means for outputting the clock of N phase shifted by T2 time each for which the cycle T1 of the clock of a prescribed frequency is divided by N; a means for sampling serially transferred data at every T2 time; a means for converting sampled data to first N-bit parallel data in every cycle T1; a means for performing conversion to second N-bit parallel data indicating the data change point of the sampled data; and a means for outputting third N-bit parallel data indicating the roughly intermediate position of the data change point of the serial data with the second N-bit parallel data as phase information input. The bit position data of the first N-bit parallel data same as the bit position indicated by the third N-bit parallel data are turned to restoration data. <P>COPYRIGHT: (C)2009,JPO&INPIT |
