发明名称 STRUCTURE AND METHOD FOR IMPLEMENTING POWER SAVING IN ADDRESSING OF DRAM ARCHITECTURE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a structure and a method for implementing power saving in addressing of a DRAM device. <P>SOLUTION: A random access memory device includes an array of individual memory cells arranged into rows and columns, and each memory cell has a corresponding access device. Assuming N as the number corresponding to the number of independently accessible partitions of the array, each row of the array further includes a corresponding plurality of N word lines, and each access device in a given row is coupled to only one of the N word lines of the rows. An address decoder communicating with the array receives a plurality of row address bits, and determines which of the N partitions in a requested row must be accessed on the requested row identified by the row address bits, and does not activate the access device within the selected row but not within the partition to be accessed. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2008234662(A) 申请公布日期 2008.10.02
申请号 JP20080074311 申请日期 2008.03.21
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 GERMANN PHILIP RAYMOND;BORKENHAGEN JOHN M;BECKER DARRYL J;BARTLEY GERALD KEITH;HOVIS WILLIAM PAUL
分类号 G06F12/06;G06F1/32;G11C11/401;G11C11/407 主分类号 G06F12/06
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