| 摘要 |
A method for forming an isolation layer of a semiconductor memory device is provided to uniformly control coupling rate of the device by regularly controlling a height of the isolation layer. A tunnel dielectric(101), a conductive layer(102) for a floating gate, and a dielectric for a hard mask are sequentially formed on a semiconductor substrate(100). The dielectric for a hard mask is thicker that another end of a wafer. The dielectric for a hard mask, the conductive layer for a floating gate, the tunnel dielectric, and the semiconductor substrate are selectively etched by performing an etching process to form a trench(104). A dielectric is formed on the whole structure including the trench. A planarization process is performed to expose an upper portion of the dielectric for a hard mask and to form an isolation layer. After the dielectric for a hard mask is removed, an etching process is performed to etch an upper end of the isolation layer to control EFH(Effective Field oxide Height). The end of the wafer is contacted to an etch solution earlier than the other end thereof.
|
