| 摘要 |
A semiconductor memory device is provided to ensure a tRCD(RAS to CAS delay) margin by reducing bit line capacitance according to division of bit line pairs in a cell mat during amplification of a bit line sense amplifier. A semiconductor memory device includes a bit line separation unit(12) and a bit line sense amplifier(30). The bit line separation unit separates bit lines selectively according to a bit line separation control signal. The bit line sense amplifier senses and amplifies data loaded on the bit lines. |
