发明名称 Delay locked loop and method for setting a delay chain
摘要 Each of the phase detector cells (31,51,71,91) in a phase detector (2) has an input (32,52,72,92) connected to a node (11) and another input (33,53,73,93) connected to an output (35,55,75,95) of a corresponding delay cell (30,50,70,90) in a delay circuit (1). The phase detector is coupled to a control unit (4) that adjusts the delay time of the delay circuit by switching the delay cells.
申请公布号 KR100861340(B1) 申请公布日期 2008.10.01
申请号 KR20060045456 申请日期 2006.05.22
申请人 发明人
分类号 H03L7/00 主分类号 H03L7/00
代理机构 代理人
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