METHODS OF FORMING CMOS INTEGRATED CIRCUIT DEVICES HAVING STRESSED NMOS AND PMOS CHANNEL REGIONS THEREIN AND CIRCUITS FORMED THEREBY

摘要

A method for manufacturing an integrated circuit device, a method for manufacturing a semiconductor device, and a semiconductor device manufactured thereby are provided to form stably a contact plug in an inside of a contact hole formed on an upper surface of a silicide layer or in the silicide layer. A first, second, and third transistors are formed on a semiconductor substrate(100). The first and second transistors are covered with a first electrical insulating layer having a high internal stress characteristic to apply tensile stress or compressive stress to a channel region of the first transistor. The second and third transistors are covered with a second electrical insulating layer having a high internal stress characteristic to apply tensile stress or compressive stress to a channel region of the third transistor. A first opening is defined by the second electrical insulating layer by removing selectively a first region of the second electrical insulating layer to be extended in a gate electrode side of the second transistor. A first opening extended through the first electrical insulating layer and a second opening extended through the second electrical insulating layer are defined by removing selectively a first region of the first electrical insulating layer and a second region of the second electrical insulating layer.