发明名称 |
Semiconductor device and manufacturing method thereof |
摘要 |
A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.
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申请公布号 |
US7429770(B2) |
申请公布日期 |
2008.09.30 |
申请号 |
US20050037333 |
申请日期 |
2005.01.19 |
申请人 |
RENESAS TECHNOLOGY CORP.;TOKYO ELECTRON LIMITED;OKY ELECTRIC INDUSTRY CO., LTD. |
发明人 |
KADOSHIMA MASARU;AKIYAMA KOJI;OHNO MORIFUMI |
分类号 |
H01L21/28;H01L29/76;H01L21/3205;H01L21/336;H01L21/338;H01L21/768;H01L21/8238;H01L27/092;H01L29/423;H01L29/49;H01L29/51;H01L29/78;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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地址 |
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