发明名称 |
Zeroing circuit for performance counter |
摘要 |
In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits ("MSBs") of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.
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申请公布号 |
US7430696(B2) |
申请公布日期 |
2008.09.30 |
申请号 |
US20030635079 |
申请日期 |
2003.08.06 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
ADKISSON RICHARD W.;JOHNSON TYLER |
分类号 |
G01R31/28;G06F11/00;H02H3/05 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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