| 摘要 |
<p>A semiconductor and a manufacturing method thereof are provided to improve a GIDL(Gate Induced Drain Leakage) characteristic by forming a lower gate electrode with a stacked structure of a p+ polysilicon layer and a p+ polysilicon germanium layer. A fin type active region is defined on a semiconductor substrate(210) including an isolation structure. A recess is formed on the fin type active region. A gate electrode including a silicon germanium layer for burying the recess is formed on the pin type active region. An LDD region is formed on the semiconductor substrate corresponding to both sides of the gate electrode. The gate electrode includes an upper gate electrode and a lower gate electrode(250). The lower gate electrode includes a stacked structure of a p+ polysilicon layer(252) and a p+ polysilicon germanium layer(254).</p> |
