| 摘要 |
A clock data restoring device (1) restores a clock signal and data based on an inputted digital signal. The clock data restoring device is provided with an equalizer section (10), a sampler section (20), a clock generating section (30), an equalizer control section (40) and a phase monitor section (50). A level adjustment quantity of the digital signal at the equalizer section (10) is controlled by loop processing by the equalizer section (10), the sampler section (20) and the equalizer control section (40). On the other hand, when a phase difference between a clock signal (CK) and the digital signal is larger than a prescribed value, the control is stopped by the phase monitor section (50). Thus, the clock signal and the data are more correctly restored.
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