| 摘要 |
A method for manufacturing a semiconductor device is provided to reduce a line width of a bit line contact hole region by performing a resist reflow process after forming a photoresist layer pattern for defining a bit line contact hole region. An interlayer dielectric(140), a hard mask layer, and a barrier layer(150) are formed on an upper portion of a semiconductor substrate(100). An anti-reflective layer and a photoresist layer pattern(160) defining a contact region are formed on an upper portion of the barrier layer. The anti-reflective layer is etched by using the photoresist layer pattern as a mask to form an anti-reflective layer pattern. The anti-reflective layer pattern has a positive slope. The photoresist layer pattern is removed. The barrier layer, the hard mask layer, and the interlayer dielectric are etched by using the anti-reflective layer pattern as an etching mask to form a contact hole. The interlayer dielectric is a BPSG(Boro-Phospho-Silicate-Glass) oxide layer.
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