| 摘要 |
<P>PROBLEM TO BE SOLVED: To enable a synchronizing component having a stable period to be extracted even when an input signal has an unstable period. <P>SOLUTION: An input signal is judged for a logical value by a logic threshold variable input buffer 101. The buffer 101 outputs a signal of a logical value High or a logical value Low in response to its judged result. The threshold level of the logical value judgment of the buffer 101 is regulated via a feedback circuit 104 according to a comparison result of the times of the logical values High and Low of an H/L pulse length detector 103. A pulse signal having a stable period is obtained from a signal change detecting circuit 102 for detecting a change in the output signal of the buffer 101 to output the pulse signal having a predetermined width as a synchronizing component. <P>COPYRIGHT: (C)2004,JPO |
