| 摘要 |
Reducing the switching losses on an interconnect at a receiving device 100 by preventing switching activity in a data reception unit 116 (218, fig 2) based upon a determination made within a data suppression unit 106 (206, fig 2) that the data on data lines 104 or on shared address/data lines in a data cycle is not addressed to that device. The data suppression unit may include a multiplexer 110 or AND logic gates (210-214, fig 2) to suppress the supply of data on lines 114 (214, fig 2) to the data reception unit. The data suppression logic may also include address decode logic 108 to decode received addresses and determine if the target address of a transmission is local to the device. When the target address is local to the device the address decode enables the multiplexer or AND logic gates to pass the data to lines 114 to the data reception unit. The interconnect may be a PCI bus or a USB. The system/method is suitable for use with both serial and parallel interconnects, both buses internal to the computer and for interconnections to external devices. The interconnect may have separate address and data lines or shared address/data lines and a broadcast protocol may be used. In the case of data and address communicated over the same lines the address cycle precedes the data cycle and therefore the input to the data reception unit can be suppressed for the duration of the data cycle after a determination that the address is not local to that device during the address cycle. |
