| 摘要 |
A PLL circuit having an analog-to-digital converter; a phase error detecting circuit; and an oscillator, in which the phase error detecting circuit includes: phase error detecting means detecting a phase error from a data stream signal and a data stream signal 1 clock cycle earlier; absolute value comparing means detecting an absolute value of the phase error detected exceeding a predetermined threshold; holding means holding a polarity of the phase error, as of a timing of the detection by the absolute value comparing means, for a period of the detection; anticoincidence detecting means detecting anticoincidence between the polarity held by the holding means and a polarity of the phase error detected by the phase error detecting means; and polarity inverting means that provides the phase error detection signal by inverting the polarity of the phase error in detection of anticoincidence, or without inverting the polarity in detection of no anticoincidence.
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