发明名称 Phase-locked loop synthesizer
摘要 A PLL synthesizer includes a reference oscillator, an controllable oscillator which generates an oscillation signal which varies in frequency according to a control signal, a phase comparator, and a loop filter. The loop filter includes an A/D converter, a digital filter, and a D/A converter. The digital filter removes high-frequency components from the output of the A/D converter according to setting data. The digital filter is set to a filter characteristic depending to a selected frequency of the oscillation signal. The digital output signal of the digital filter is converted to an analog signal which is used as the control signal of the controllable oscillator.
申请公布号 AU1631097(A) 申请公布日期 1997.09.18
申请号 AU19970016310 申请日期 1997.03.14
申请人 NEC CORPORATION 发明人 KATSUHIRO ISHII
分类号 H03L7/18;H03L7/089;H03L7/093;H03L7/095;H03L7/107;H03L7/183 主分类号 H03L7/18
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