| 摘要 |
PROBLEM TO BE SOLVED: To optimize a difference of bit line signal volumes when reading a memory array. SOLUTION: The bit line BL and bit line/BL are connected to a sense amplifier 4 at the periphery of a memory cell array of the ferroelectric substance memory. The memory cell MC1 to memory cell MCm, a bit line insertion capacitance Cb1 and a bit line parasitic capacitance Ck1 are connected to the bit line BL. The bit line parasitic capacitance Ck1 is the parasitic capacitance formed between the bit line BL and low voltage power supply (ground potential), and consists of a capacitance between adjacent bit lines and a diffusion layer capacitance of memory cell transistors. The bit line insertion capacitor Cb1 consists of the ferroelectric substance film, and whose one end is connected to the bit line BL and the other end to the low voltage power supply (ground potential) Vss to play a role of setting the bit line capacity to an optimum value. COPYRIGHT: (C)2008,JPO&INPIT
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