| 摘要 |
<p>A PLL frequency synthesizer for realizing high-speed operation in frequency synthesizer with small channel interval, causing the reference frequency to raise at the time of changing, exception for influence to noise characteristic. There are provided a plurality (n-systems) of phase comparators (2.1, 2.2, 2.n), feedback frequency dividers (6.1, 6.2, 6.n), and reference signal frequency dividers (8.1, 8.2, 8.n), and a timing generating section (9) for outputting signal causing each system of frequency divider to render enable every cycle of nX DELTA f, and the OR gate for superposing each phase comparison signal. Each phase comparison signal is sent to the charge pump (3) by a cycle of nX DELTA f, and the reference frequency is capable of being raised by n times of channel interval. Further the control section monitors lock detection of each phase comparator (2.1, 2.2, 2.n), thus implementing voltage control of each phase comparison system, and then when it arrives at convergence-synchronization, all systems of power source make OFF exception for the phase comparison system proceeding the lock signal in the first place, thus changing the reference frequency according to only phase comparison system into loop to be dropped to DELTA f. <IMAGE></p> |
