| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of expanding an oscillation frequency range while maintaining a low jitter. <P>SOLUTION: The PLL circuit is equipped with: a regulator 21; a phase frequency comparator 22; a charge pump 23; a supply voltage control part 24 which outputs a predetermined control signal to the regulator to control an output voltage of the regulator; a first path setting part 25-1 which switches an output of the phase frequency comparator from the charge pump to the supply voltage control part in power application or a predetermined test mode; a low pass filter 23 which outputs a first control voltage; a control voltage generation circuit 27 which outputs a second control voltage; a voltage control oscillator 28 which outputs an output clock according to the first, the second control voltage and the output voltage of the regulator; a second path setting part 25-2 which switches the control voltage inputted in a control terminal of the voltage control oscillator from the first control voltage to the second control voltage in the power application or the predetermined test mode and a frequency divider 29. <P>COPYRIGHT: (C)2008,JPO&INPIT |
