发明名称 COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER
摘要 A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after out-of-order execution when at least one of the plurality of processors is in an Instruction Level Parallelism (ILP) mode and at least one of the plurality of processors has a Thread Level Parallelism (TLP) core; detecting an imbalance in a dispatch of instructions of a first dependence chain compared to a dispatch of instructions of a second dependence chain with respect to dependence chain priority; determining a source of the imbalance; and activating the ILP mode when the source of the imbalance has been determined.
申请公布号 US2008229077(A1) 申请公布日期 2008.09.18
申请号 US20080127845 申请日期 2008.05.28
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 SATHAYE SUMEDH W.
分类号 G06F9/30 主分类号 G06F9/30
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