| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay clock circuit having transistor variation tolerance without inviting an increase in circuit area. SOLUTION: In the delay clock circuit 16 for delaying an input clock signal, components having first and second inverters 12 and 13 connected in series are cascaded. A delay clock control circuit 14 operates so as to make a through current flow to a connection node of the first and the second inverters 12 and 13 to cause charge contention for a predetermined period of time during the transition of an input of the components. The delay clock control circuit 14 is arranged between a power supply line VDD and the connection node, and is provided with a first P type transistor 15 for receiving an output of the second inverter 13 at a gate. COPYRIGHT: (C)2008,JPO&INPIT
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