| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock gated circuit capable of solving the problem of power consumption caused by causing unnecessary electric charge from a discharging unit into a fighting node to flow in. SOLUTION: A clock gated circuit is disclosed. The clock gated circuit of the present invention includes a clock signal receiving unit that applies a first voltage to a fighting node in a section where the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic in a section where the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power voltage or ground voltage; and an output unit that inverts a logic level of voltage of the fighting node to generate the gated clock signal. The first logic may be logic low and the first voltage may be a power voltage, A blocking unit blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. COPYRIGHT: (C)2008,JPO&INPIT
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