CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device which achieves stable operation without varying a frequency during a self-running period during a synchronization period or after the end of the synchronization period caused by variations in manufacturing processes.

SOLUTION: The semiconductor device is provided with a clock signal generation circuit that includes: a reference clock signal generation circuit which generates a first reference clock signal; a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal; a second counter circuit which counts the number of rising edges of the first reference clock signal by using the enumerated value of the first counter circuit; a first divider circuit which divides the frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides the frequency of the second reference clock signal and generates a clock signal.

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