| 摘要 |
PROBLEM TO BE SOLVED: To provide a serial interface circuit capable of easily changing the alignment order of data to be serially output. SOLUTION: When a data signal DT is output by designating an address "X" with the use of an address signal AD, the data signal DT is held in a transmission buffer 14 at the timing of a writing control signal WT, a "0" signal ADY is held in an FF 15, and a selection signal SL is made to be "0". Thus, serial data SO is output from a shift register 20 sequentially from the LSB of the data signal DT. When an address "Y" is designated with the use of an address signal AD, a "1" signal ADY is held in the FF 15 and the selection signal SL is made to be "1". Thus, the serial data SO is output from the shift register 20 sequentially from the MSB of the data signal DT. COPYRIGHT: (C)2008,JPO&INPIT |
