| 摘要 |
A device (100) is disclosed having a first Field Effect Transistor (102) having a channel region controlled by a gate (108, 110), a second Field Effect Transistor (104) having a first channel region substantially controlled by a first gate (112), and a second channel region substantially controlled by a second gate (122). The gate (108, 110) of the first Field Effect Transistor and the first gate (112) of the second Field Effect Transistor are coupled to a memory write line. The second gate (112) of the second Field Effect Transistor receives a control signal from a memory bit cell.
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