发明名称 CLOCK REDUNDANCY DEVICE
摘要 <p>In order to synchronize the phase of a clock made redundant from an input clock more accurately, a first unit branches the input clock into first and second clocks, and a second unit delivers the second clock through a first element for interrupting the impact of the first unit. A phase regulation circuit constituting the first unit synchronizes the phase of the first clock with the phase of the second clock passing a second element having operating characteristics identical to those of the first element.</p>
申请公布号 WO2008111171(A1) 申请公布日期 2008.09.18
申请号 WO2007JP54947 申请日期 2007.03.13
申请人 FUJITSU LIMITED;OKU, TATSUYA;HASHIZUME, MASATO;NISHIDA, HIROSHI 发明人 OKU, TATSUYA;HASHIZUME, MASATO;NISHIDA, HIROSHI
分类号 H04L7/00;G06F1/04 主分类号 H04L7/00
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