发明名称 Trace optimization in flattened netlist by storing and retrieving intermediate results
摘要 A method of trace optimization in a flattened netlist of a circuit is disclosed. The method generally includes the steps of (A) generating a first total result by tracing a first path through the flattened netlist, (B) writing an intermediate result in a memory, the intermediate result characterizing a module having a plurality of instances in the circuit, (C) adding the intermediate result as read from the memory to the first total result upon crossing each of the instances of the module along the first path and (D) writing the first total result into the memory.
申请公布号 US2008229268(A1) 申请公布日期 2008.09.18
申请号 US20070724143 申请日期 2007.03.14
申请人 LSI LOGIC CORPORATION 发明人 RANGASAMY UMESH;ADIGA SRINIDHI
分类号 G06F17/50 主分类号 G06F17/50
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