| 摘要 |
Each cell comprises a first selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; a second selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; an arithmetic and logic unit which accepts selection output of the first selector and selection output of the second selector in N bits (N is a natural number of 2 or more), and performs a logic operation that is selected from a plurality of logic operations on accepted data of N bits; a selection controller which supplies, to the first selector and the second selector, a data selection control signal for indicating data to be selected; and an ALU controller which supplies, to the arithmetic and logic unit, an ALU control signal that designates the logic operation to be executed. The first selector, the second selector, and the arithmetic and logic unit are capable of reconfiguration based on the selection control signal and the ALU control signal. The first selector and the second selector rearranges M[i] bits of i-th data in a prescribed order based on the selection control signal, and outputs the rearranged data (i is a natural number that satisfies i<=K, and M[i] is an integer that satisfies Sigma<SUB>i=1</SUB><SUP>K</SUP>M[i]<=N).
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