发明名称 MULTILAYER PRINTED WIRING BOARD AND ITS MANUFACTURING METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To restrain core layer vias from inducing high impedance by narrowing an interval between core layer vias. <P>SOLUTION: In this method for manufacturing a multilayer printed wiring board, the core layer vias having a cylindrical conductive layer are so formed that conductive parts contact with each other, and then hole-punch working is performed along an axis of symmetry of the four core layer vias while penetrating a core substrate, to form through holes having a predetermined diameter, thereby the core layer vias 11, 11, ... separated from each other are formed. The through hole is filled with an insulator. Along a center axis of the through hole filled with the insulator, hole-punch working is so performed as to penetrate the core substrate to form through holes having a predetermined diameter smaller than that of the former through hole. A conductive layer is formed on the inner wall surface of the through hole to form a core layer via 9. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008218931(A) 申请公布日期 2008.09.18
申请号 JP20070057926 申请日期 2007.03.07
申请人 NEC CORP 发明人 TAKEDA TSUTOMU
分类号 H05K3/46 主分类号 H05K3/46
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