| 摘要 |
PROBLEM TO BE SOLVED: To enable error correction of defects of two bits or more without increasing chip area, in a memory provided with an error correction circuit. SOLUTION: Respective switches 103 provided respectively at respective pairs of bit lines BL, XBL switch and control connection and no-connection of the pair of bit lines BL, XBL and either of the pair of data lines DL, XDL according to a signal of any one column selection YS. The pair of bit lines BL, XBL , the pair of data lines DL, XDL, and the column selection line YS are composed so that the respective pairs of bit lines BL, XBL connected to a plurality of pairs of data lines DL, XDL through a column switch 103 group relating to one column selection line YS and memory cells 101 provided respectively at cross points with one word line WL are not made to be adjacent to each other in corresponding relationship. COPYRIGHT: (C)2008,JPO&INPIT
|
