| 摘要 |
PROBLEM TO BE SOLVED: To provide a static timing analysis method for reducing the number of operations of static timing analysis, for reducing man-hours by eliminating the need of manual settings of timing restruction, and for improving reliability. SOLUTION: Specifications of a PLL (phase-locked loop) circuit is integrated into a library (S1). The PLL circuit in a net list 13 and its reference clock frequency are automatically extracted (S2). An output frequency fluctuation of the PLL circuit and a stationary phase error are automatically extracted (S3). When there is a division circuit in a feedback path of the PLL circuit, an output frequency fluctuation after division is automatically calculated (S4), and clock dispersion and latency of a PLL output clock are automatically calculated (S5). Based on a result of the step S5, static timing analysis is carried out (S6). COPYRIGHT: (C)2008,JPO&INPIT
|
