A METHOD OF MAKING RELIABLE WAFER LEVEL CHIP SCALE PACKAGE SEMICONDUCTOR DEVICES

摘要

The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using a highly compressive insulating material is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.