发明名称 |
Address translation system for use in a simulation environment |
摘要 |
Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of virtual addresses required for execution of the system definition file in a virtual testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a physical memory space for a testable system. The method further includes generating translation information by translating the virtual addresses into physical addresses using the memory map file.
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申请公布号 |
US2008229165(A1) |
申请公布日期 |
2008.09.18 |
申请号 |
US20070724827 |
申请日期 |
2007.03.16 |
申请人 |
ETAS, INC.;ROBERT BOSCH GMBH |
发明人 |
FOSTER TIMOTHY W.;CATES JAMEY JOSEPH |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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