| 摘要 |
<p>According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell (40) by an operation to read a replica cell (71) to which a replica bit line (TBL) having a load equivalent to a bit line to be connected to the memory cell (40) and a replica word line (TWL) are connected, the semiconductor memory device comprising: a write control signal generating unit (80) that includes logic gates coupled in multi stages for receiving an input of a replica word line activating signal (S1) generated in response to a driving signal for driving the replica word line, the write control signal generating unit (80) generating a write control signal (S2) to determine a data write time required to write data in the memory cell (40) based on the replica word line activating signal (S1).</p> |
