Clock signal generator circuit using a logical result of an output of a counter and a source clock to generate plurality of clock signals

摘要

A clock signal generator circuit has a clock generator for generating clock signals to be supplied to a central processing unit and to functional blocks, and clock selectors. The clock generator divides the frequency of a source clock signal, to form a clock signal having an optional period. Namely, the clock generator suppresses at least one active or inactive state of the source clock signal, to generate a clock signal whose period is an integer multiple of that of the source clock signal. The clock selectors receive the clock signals generated by the clock generator and selectively supply them to the CPU and functional blocks. The clock signal generator circuit is capable of operating a microcontroller system at a required minimum speed, to optimize the power consumption of the system.