| 摘要 |
<p>The device has an encoding unit (100) comprising an input to provide an input data word (X), an output to provide an encoded original data word (Y) and an encoding block (10). The encoding block has multiple encoding stages (1-1, 1-2, 1-d) switched one behind the other between the input and the output. The stages exhibit parallelly switched logic blocks, where data bits of the input data word are provided to the logic blocks of the encoding stage (1-1) and data bits of the output data word of the preceding encoding stage are supplied to the logic blocks of the encoding stages (1-2, 1-d). The logic blocks are selected from an inverting multiplexer, NAND gate or NOR gate.</p> |
