发明名称 Memory bus arbitration using memory bank readiness
摘要 A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.
申请公布号 US7426603(B2) 申请公布日期 2008.09.16
申请号 US20060499015 申请日期 2006.08.04
申请人 发明人
分类号 G06F12/00 主分类号 G06F12/00
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