发明名称 Circuit arrangement and method for driving electronic chips
摘要 The invention provides a method for testing circuit units to be tested in a test apparatus, different identification units being assigned to the circuit units to be tested, the circuit units to be tested being connected to the test apparatus, a tester data stream including command blocks being output from the test apparatus, the tester data stream being compared with the identification units, the circuit unit to be tested, the identification unit of which matches the tester data stream output by the test apparatus, being activated and at least one command block for this circuit unit to be tested being processed in the circuit unit to be tested, whereupon the circuit unit to be tested is deactivated.
申请公布号 US7426669(B2) 申请公布日期 2008.09.16
申请号 US20040853768 申请日期 2004.10.14
申请人 INFINEON TECHNOLOGIES AG 发明人 FLACH BJOERN;LOGISCH ANDREAS;RUF WOLFGANG;SCHITTENHELM MICHAEL;SCHNELL MARTIN
分类号 G01R31/28;G01R31/317;G11C29/16 主分类号 G01R31/28
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