| 摘要 |
The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. At the end of a CRC error detection division operation, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.
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