发明名称 PLL noise smoothing using dual-modulus interleaving
摘要 The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, "ones" and "tens" are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.
申请公布号 US7424083(B2) 申请公布日期 2008.09.09
申请号 US20050202387 申请日期 2005.08.10
申请人 发明人
分类号 H03K21/00 主分类号 H03K21/00
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