发明名称 Method and Apparatus of Stress Relief in Semiconductor Structures
摘要 A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
申请公布号 US2008213993(A1) 申请公布日期 2008.09.04
申请号 US20080098976 申请日期 2008.04.07
申请人 HOINKIS MARK;HIERLEMANN MATTHIAS;FRIESE GERALD;COWLEY ANDY;WARNER DENNIS J;KALTALIOGLU ERDEM 发明人 HOINKIS MARK;HIERLEMANN MATTHIAS;FRIESE GERALD;COWLEY ANDY;WARNER DENNIS J.;KALTALIOGLU ERDEM
分类号 H01L21/4763;H01L23/522 主分类号 H01L21/4763
代理机构 代理人
主权项
地址