发明名称 ANALOG/DIGITAL CONVERTER
摘要 PROBLEM TO BE SOLVED: To provide a pipeline type A/D converter having a configuration for averting the reduction in the yield of an A/D converter due to the offset abnormality of a comparator. SOLUTION: The pipeline type A/D converter is provided with first to N-th (where N is an integer of 2 or larger) stages (10<SB>1</SB>to 10<SB>N</SB>) which are cascade connected, and convert an analog signal inputted from the preceding stage into a digital signal of prescribed bits and output the digital signal. Each of the first to the (N-1)-th stages (10<SB>1</SB>to 10<SB>N-1</SB>) is provided with an analog/digital conversion circuit, including a comparator for comparing the analog signal with predetermined reference potentials different from one another in parallel. The first to the (N-1)-th stages are a redundant configuration, in which comparators of the stages are provided with a spare comparator and are provided with a comparator selection circuit (40) for outputting a comparator selection signal for selectively activating one of comparators of the redundant configuration. When a comparator of the redundant configuration is determined as being a comparator whose offset exceeds permissible value, a comparator whose offset exceeds the permissible value is replaced by a spare comparator on the basis of the comparator selection signal. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008205824(A) 申请公布日期 2008.09.04
申请号 JP20070039623 申请日期 2007.02.20
申请人 NEC ELECTRONICS CORP 发明人 MATSUBAYASHI TOMOYA
分类号 H03M1/10;H03M1/14 主分类号 H03M1/10
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