| 摘要 |
PROBLEM TO BE SOLVED: To reduce a design period by easily executing high-accuracy characteristic extraction along an actual device pattern in short TAT (Turn Around Time). SOLUTION: A position having a difference between an actual pattern and a layout pattern of a semiconductor integrated circuit is detected (ST11), a characteristic value is corrected only in the position having the difference to perform the characteristic extraction (ST14), and the characteristic extraction is performed from the layout pattern in a position except the position having the difference (ST13). COPYRIGHT: (C)2008,JPO&INPIT
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